Architecture for Video SoC development

The list is discussed the performance of ASIC, FPGA and DSP w. core listed in tabla 1. Table 2 can be shown as a sample to design the algorithm what, how should be analyzed.

Table 1: SoC table

The idea will be a ASIC for highly os and operation controller i.e., communications, LED, keypad and flow handling equipped with a MCU(X86, ARM). The FPGA is acted like a pixel to pixel manipulation and pipline streaming. Combination from ASIC MCU+FPGA is good to apply the instrument market.

Algorithm porting need to be analyzed like this. The following table summarizes the difference between MPEG2 main profile (MP), MPEG4 Advanced simple profile (ASP) and H.264 high profile (HP).

Table 2: MPEG2, MPEG4, H.264 table








Chip-Integrated solution sought

To reduce the size of the imaging module, the industry also badly needs an integrated solution: a CMOS imaging sensor integrated with an image preprocessor. The first stage of imaging signal processing" — RGB to YUV conversion — onto the sensor chip. While the others can try have tried to integrate a similar image processor onto an imaging sensor die, but problems found it impossible to do so without degrading pictures, because the power dissipation of the image processor gets too high and affects the noise level of the whole sensor.